1. Field of the Invention
This present invention generally relates to the field of semiconductor power devices. More particularly, the present invention relates to a method for mending lattice defects in a power MOSFET with a super-junction.
2. Description of the Prior Art
A power device is mainly used in power management; for instance, in a switching power supply, a management integrated circuit in the core or a peripheral region of computer, a backlight power supply, and in an electric motor control. The type of power devices described above include an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), and a bipolar junction transistor (BJT), among which the MOSFET is the most widely applied because of its energy saving properties and ability to provide faster switch speed.
In one kind of power device, a P-type epitaxial layer and an N-type epitaxial layer are alternatively disposed to form several PN junctions inside a body, wherein the junctions are vertical to a surface of the body. A structure with the described PN junctions is also called a super-junction structure. In a conventional method for fabricating the super-junction structure, an epitaxial layer of a first conductivity type, e.g. N-type, is formed on a substrate of the first conductivity type. Then, a plurality of trenches is etched into the first conductivity type epitaxial layer by a first mask. A second conductivity type epitaxial layer, e.g. P-type epitaxial layer, is filled into the trenches and the surface of the second conductivity type epitaxial layer is made level with the surface of the first conductivity type epitaxial layer. Hence, the trenches are filled with the second conductivity type epitaxial layer and are surrounded by the first conductivity type epitaxial layer. As a result, a super-junction structure with a plurality of PN junctions is formed.
The above-mentioned method has many drawbacks, however. For instance, defects, such as seam defects, void defects and lattice dislocation, often form inside the second conductivity type epitaxial layer during the fabrication process. As a result, the defects reduce the yield and conductivity of the device. In light of the above, there is still a need for fabricating a semiconductor power device with fewer lattice defects, which are capable of overcoming the shortcomings and deficiencies of the prior art and further increasing the yield of the device.